View XRD8799_5742953.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux february 2001 rev. 1.00 features ? 10-bit resolution ? 8-channel mux ? sampling rate - < 1khz - 2mhz ? low power cmos - 35 mw (typ) ? power down; lower consumption - 0.8 mw (typ) ? input range between gnd and v dd ? no s/h required for analog signals less than 100khz ? no s/h required for ccd signals less than 2mhz ? single power supply (4.5 to 5.5v) ? latch-up free ? esd protection: 2000 volts minimum applications ? m p/dsp interface and control application ? high resolution imaging - scanners & copiers ? wireless digital communications ? multiplexed data acquisition benefits ? reduced board space (small package) ? reduced external parts, no sample/hold needed ? suitable for battery & power critical applications ? designer can adapt input range & scaling general description the XRD8799 is a flexible, easy to use, precision 10- bit analog-to-digital converter with 8-channel mux that operates over a wide range of input and sampling conditions. the XRD8799 can operate with pulsed "on demand" conversion operation or continuous "pipeline" operation for sampling rates up to 2mhz. the elimination of the s/h requirements, very low power, and small package size offer the designer a low cost solution. no sample and hold is required for ccd applications up to 2mhz, or multiplexed input applications when the signal source bandwidth is lim- ited to 100khz. the input architecture of the XRD8799 allows direct interface to any analog input range between agnd and av dd (0 to 1v, 1 to 4v, 0 to 5v, etc.). the user simply sets v ref(+) and v ref(-) to encompass the desired input range. scaled reference resistor taps @ 1/4 r, 1/2 r and 3/4 r allow for customizing the transfer curve as well as providing a 1/2 span reference voltage. digital out- puts are cmos and ttl compatible. the XRD8799 uses a two-step flash technique. the first segment converts the 5 msbs and consists of autobalanced comparators, latches, an encoder, and buffer storage registers. the second segment con- verts the remaining 5 lsbs. when the power down input is "high", the data out- puts db9 to db0 hold the current values and v ref(-) is disconnected from v ref1(-) . the power consumption during the power down mode is 0.1mw. ordering information p a r t n u m b e r p a c k a g e o p e r a t i n g t e m p e r a t u r e r a n g e XRD8799aiq pqfp -40 c to +85 c
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 2 f i g u r e 1. s i m p l i f i e d b l o c k d i a g r a m a n d t i m i n g f i g u r e 2. p i n o u t o f t h e XRD8799 ofw 10 dff n n clk fine comparators adder 5 6 5 clk r2 r1 f b dgnd coarse comparators n ofw resolution n-1 n-1 av dd dv dd v ref(+) db9-db0 db9-db0 1 or 8 mux a in1 a in8 f s 3 to 8 decoder a1 a0 wr av dd oe a2 clr agnd v ref1(-) pd r3 ladder v ref(-) latch 8 f b f s pin configurations see packaging section for package dimensions 33 23 22 12 1 11 34 44 index 44-pin pqfp (10mm x 10mm)
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 3 pin descriptions p i n # n a m e d e s c r i p t i o n 1 db6 data output bit 6 2 db7 data output bit 7 3 dgnd digital ground 4 dgnd digital ground 5 dv dd digital v dd 6 clr clear (active low) 7 wr write (active low) 8 a2 address 2 9 a1 address 1 10 a0 address 0 11 clk clock input 12 oe output enable (active low) 13 n/c no connect 14 db8 data output bit 8 15 db9 data output bit 9 (msb) 16 ofw overflow output 17 v ref(+) upper reference voltage 18 v ref(-) lower reference voltage 19 v ref1(-) lower reference voltage 20 r1 reference ladder tap 21 r2 reference ladder tap 22 a in8 analog signal input 8 p i n # n a m e d e s c r i p t i o n 23 r3 reference ladder tap 24 n/c no connect 25 a in1 analog signal input 1 26 a in2 analog signal input 2 27 a in3 analog signal input 3 28 a in4 analog signal input 4 29 a in5 analog signal input 5 30 agnd analog ground 31 av dd analog v dd 32 av dd analog v dd 33 a in6 analog signal input 6 34 agnd analog ground 35 pd power down 36 a in7 analog signal input 7 37 db0 data output bit 0 (lsb) 38 db1 data output bit 1 39 db2 data output bit 2 40 db3 data output bit 3 41 db4 data output bit 4 42 db5 data output bit 5 43 n/c no connect 44 n/c no connect
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 4 t a b l e 1: t r u t h t a b l e f o r i n p u t c h a n n e l s e l e c t i o n n o t e : clr , wr , a2, a1, a0 are internally connected to ground through 500k w resistance. clr wr a2 a1 a0 s e l e c t e d a n a l o g i n p u t l x x x x a in1 h l l l l a in1 h l l l h a in2 h l l h l a in3 h l l h h a in4 h l h l l a in5 h l h l h a in6 h l h h l a in7 h l h h h a in8 h h x x x previous selection
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 5 electrical characteristics e l e c t r i c a l c h a r a c t e r i s t i c s av dd = dv dd = 5 v, f s = 2 mh z (50% d u t y c y c l e ), v ref(+) = 4.6, v ref(-) = agnd, t a = 25 c, u n l e s s o t h e r w i s e s p e c i f i e d p a r a m e t e r s y m b o l m i n t y p m a x u n i t s t e s t c o n d i t i o n s /c o m m e n t s k e y f e a t u r e s resolution 10 bits sampling rate fs .001 2.0 mhz for rated performance a c c u r a c y (a g r a d e ) 2 differential non-linearity dnl -1 + 0.3 1 lsb integral non-linearity inl 1 2 lsb best fit line (max inl - min inl)/2 zero scale error ezs 0 50 100 mv full scale error efs 0 30 60 mv r e f e r e n c e v o l t a g e s positive ref. voltage 5 v ref(+) 1.0 4.0 av dd v negative ref. voltage 5 v ref(-) agnd 1.0 av dd -1 v differential ref. voltage 5 v ref 1.0 3.0 av dd v ladder resistance rl 500 1200 2000 w a n a l o g i n p u t 1 input bandwidth (-1db) 1.0 4.0 mhz 1-channel input bandwidth (-1db) .125 0.5 mhz 8-channel input voltage range 7 v in v ref(-) v ref(+) v input capacitance 3 c in 20 pf aperture delay 1 t ap 8 ns d i g i t a l i n p u t s logical "1" voltage v ih 2.0 v logical "0" voltage v il 0.8 v leakage currents i in v in = dgnd to dv dd clk -1 1 m a clr , wr , a2, a1, a0, pd, oe -5 30 m a these input pins have 500k w internal resistors to gnd input capacitance 5 pf
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 6 clock timing clock period t s 500 1,000,000 ns rise & fall time 4 t r , t f 10 ns "high" time t b 125 250 500,000 ns "low" time t s 125 250 500,000 ns d i g i t a l o u t p u t s c out =15 p f logical "1" voltage v oh dv dd -0.5 v i load = 4 ma logical "0" voltage v ol 0.4 v i load = 4 ma tristate leakage i oz -1 1 m a v out = 0 to dv dd data hold time 1 t hld 12 ns data valid delay 1 t dl 30 35 ns write pulse width 1 t wr 40 ns multiplexer address setup time 1 t as 80 ns multiplexer address hold time 1 t ah 0 ns delay from wr to multiplexer 1 enable t muxen1 80 ns clock to pd setup time t clks1 400 ns clock to ur setup time t clks2 0 ns clock to pd hold time t clkh1 600 ns e l e c t r i c a l c h a r a c t e r i s t i c s av dd = dv dd = 5 v, f s = 2 mh z (50% d u t y c y c l e ), v ref(+) = 4.6, v ref(-) = agnd, t a = 25 c, u n l e s s o t h e r w i s e s p e c i f i e d p a r a m e t e r s y m b o l m i n t y p m a x u n i t s t e s t c o n d i t i o n s /c o m m e n t s
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 7 n o t e s : 1 guaranteed. not tested. 2 tester measures code transition voltages by dithering the voltage of the analog input (v in ). the difference between the measured code width and the ideal value (v ref /1024) is the dnl error. the inl error is the maximum distance (in lsbs) from the best fit line to any transition voltage. 3 see v in input equivalent circuit. 4 clock specification to meet aperture specification (t ap ). actual rise/fall time can be less stringent with no loss of accuracy. 5 specified values guarantee functional device. refer to other parameters for accuracy. 6 system can clock the XRD8799 with any duty cycle as long as all timing conditions are met. 7 input range where input is converted correctly into binary code. input voltage outside specified range converts to zero or full scale output. 8 dv dd and av dd are connected through the silicon substrate. connect together at the package. s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e clock to wr hold time t clkh2 0 ns power down time 1 t pd 300 ns power up time 1 t pu 200 ns data enable delay t den 14 16 ns data high z delay t dhz 4 6 ns pipeline delay (latency) 1.5 cycles p o w e r s u p p l i e s 8 power down (i dd ) i pd-dd 0.01 0.10 ma pd=high, clk high or low operating voltage (av dd , dv dd ) v dd 4.5 5.0 5.5 v current (av dd + dv dd ) i dd 7 10 ma pd=low (normal mode) e l e c t r i c a l c h a r a c t e r i s t i c s av dd = dv dd = 5 v, f s = 2 mh z (50% d u t y c y c l e ), v ref(+) = 4.6, v ref(-) = agnd, t a = 25 c, u n l e s s o t h e r w i s e s p e c i f i e d p a r a m e t e r s y m b o l m i n t y p m a x u n i t s t e s t c o n d i t i o n s /c o m m e n t s
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 8 a b s o l u t e m a x i m u m r a t i n g s : (t a = +25c u n l e s s o t h e r w i s e n o t e d ) 1, 2, 3 n o t e : 1 stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation at or above this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2 any input pin which can see a value outside the absolute maximum ratings should be protected by schottky diode clamps(hp5082-2835) from input pin to the supplies. all inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100ma for less than 100 m s. 3 v dd refers to av dd and dv dd . gnd refers to agnd and dgnd. v dd (to gnd) +7 v v ref(+) , v ref(-) , v ref(-) gnd -0.5 to v dd +0.5 v all a ins gnd -0.5 to v dd +0.5 v all inputs gnd -0.5 to v dd +0.5 v all outputs gnd -0.5 to v dd +0.5 v storage temperature -65 to +150 c lead temperature (soldering 10 seconds) +300 c package power dissipation rating to 75 c pqfp 450mw derates above 75 c 14mw/ c
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 9 f i g u r e 3. XRD8799 t i m i n g d i a g r a m theory of operation 1.0 analog-to-digital conversion the XRD8799 converts analog voltages into 1024 digital codes by encoding the outputs of coarse and fine comparators. digital logic is used to generate the overflow bit. the conversion is synchronous with the clock and it is accomplished in 2 clock periods. the reference resistance ladder is a series of resis- tors. the fine comparators use a patented interpola- tion circuit to generate the equivalent of 1024 evenly spaced reference voltages between v ref(-) and v ref(+) . the clock signal generates the two internal phases, f b (clk high) and f s (clk low = sample) (see fig- ure 1). the rising edge of the clk input marks the end of the sampling phase ( f s). internal delay of the clock circuitry will delay the actual instant when f s disconnects the latches from the comparators. this delay is called aperture delay (t ap ). the coarse comparators make the first pass conver- sion and selects a ladder range for the fine compara- tors. the fine comparators are connected to the se- lected range during the next f b phase. f i g u r e 4. XRD8799 c o m p a r a t o r s a in sampling, ladder sampling, and conversion timing figure 3 shows this relationship as a timing chart. a in sampling, ladder sampling and output data relation- ships are shown for the general case where the levels which drive the ladder need to change for each sam- pled a in time point. the ladder is referenced for both last a in sample and next a in sample at the same time. if the ladder's levels change by more than 1 lsb, one of the samples must be discarded. also note that the clock low period for the discarded a in can be reduced to the minimum t s time. auto balance clock data analog input sample n-1 sample n sample n+1 auto balance n-1 t s v ih v il v oh v ol t f t b t r t s t dl t hld t ap f s b f b f s f latch ref ladder coarse comparator s s b b f f f f latch selected range fine comparator v in v in v tap v tap
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 10 f i g u r e 5. XRD8799 c o m p a r a t o r s 1.1 a c c u r a c y o f c o n v e r s i o n : dnl a n d inl the transfer function for an ideal a/d converter is shown in figure 6. f i g u r e 6. i d e a l a/d t r a n s f e r f u n c t i o n the overflow transition (vofw) takes place at: v in = vofw = v ref(+) the first and the last transitions for the data bits take place at: v in = v001 = v ref(-) + 1.0 * lsb v in = v3ff = v ref(-) - 1.0 * lsb v ref = v ref(+) - v ref(-) lsb = v ref / 1024 = (v 3ff - v001) / 1022 n o t e : the overflow transition is a flag and has no impact on the data bits. in a "real" converter the code-to-code transitions don't fall exactly every v ref /1024 volts. a positive dnl (differential non-linearity) error means that the real width of a particular code is larger than 1 lsb. this error is measured in fractions of lsbs. a max dnl specification guarantees that all code widths (dnl errors) are within the stated value. a specification of max dnl = + 0.5 lsb means that all code widths are within 0.5 and 1.5 lsb. if v ref = 4.608 v then 1 lsb = 4.5 mv and every code width is within 2.25 and 6.75 mv. settle by clock update time reference stable time - for sample a in 1 sample a in 1 reference stable time - for sample a in 2 hold reference value past clock change for t ap time short cycle sample will be discarded sample a in 2 a in x1 not used a in x0 sample a in 1 sample a in 2 sample ladder for a in 1 sample ladder for a in x1 sample ladder for a in 2 sample ladder for a in x2 compare ladder v/s a in x0 compare ladder v/s a in 1 compare ladder v/s a in x1 compare ladder v/s a in 2 data a in 0 data a i n x0 data a in 1 data a in x1 not used not used data ladder compare (lsb bank) ladder sample window (msb bank) a in sample window clock update references external internal external t s f b f s f b f b f s f s a in x1 3ff 3fe 3fd v ref(-) v ref(+) digital codes 000 002 lsb ofw=0 v 001 ofw=1 1 lsb v001 v002 v 3fe v 3ff v 0fw =
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 11 f i g u r e 7. dnl m e a s u r e m e n t o n p r o d u c t i o n t e s t e r the formulas for differential non-linearity (dnl), in- tegral non-linearity ( in l) and zero and full scale er- rors (ezs, efs) are: dnl (001) = v002 - v001 - lsb : : : dnl (3fe) = v3ff - v3fe - lsb efs (full scale error) = v3ff - [v ref(+) -1.5 * lsb] ezs (zero scale error) = v001 - [v ref(-) + 0.5 * l sb] f i g u r e 8. r e a l a/d t r a n s f e r c u r v e figure 8 shows the zero scale and full scale error terms. figure 9 gives a visual definition of the inl error. the chart shows a 3-bit converter transfer curve with greatly exaggerated dnl errors to show the deviation of the real transfer curve from the ideal one. after a tester has measured all the transition voltag- es, the computer draws a line parallel to the ideal transfer line. by definition the best fit line makes equal the positive and the negative inl errors. for ex- ample, an inl error of -1 to +2 lsb's relative to the ideal line would be + 1.5 lsb's relative to the best fit line. f i g u r e 9. inl e r r o r c a l c u l a t i o n 1.2 c l o c k a n d c o n v e r s i o n t i m i n g a system will clock the XRD8799 continuously or it will give clock pulses intermittently when a conversion is desired. the timing of figure 10a shows normal operation, while the timing of figure 10b keeps the XRD8799 in balance and ready to sample the analog input. n + 1 n n - 1 output codes analog input (n) code width = v (n+1) - v (n) lsb = [ v ref(+) - v ref(-) ] / 1024 dnl (n) = [ v (n+1) - v (n) ] - lsb lsb dnl v (n+1) v (n) digital codes 0.5 * lsb 000 001 002 3fe 3ff v 1.5 * lsb v001 v002 v 3fe v 3ff v ref(-) v ref(+) e zs e fs 7 6 5 4 3 2 1 output codes best fit line efs ezs lsb real transfer line inl analog input (volt) ideal transfer line
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 12 f i g u r e 10. r e l a t i o n s h i p o f d a t a t o c l o c k 1.3 a n a l o g i n p u t the XRD8799 has very flexible input range character- istics. the user may set v ref(+) and v ref(-) to two fixed voltages and then vary the input dc and ac lev- els to match the vref range. another method is to first design the analog input circuitry and then adjust the reference voltages for the analog input range. one advantage is that this approach may eliminate the need for external gain and offset adjust circuitry which may be required by fixed input range a/ds. the XRD8799's performance is optimized by using analog input circuitry that is capable of driving the a in input. figure 11 shows the equivalent circuit for a in . f i g u r e 11. a n a l o g i n p u t e q u i v a l e n t c i r c u i t 1.4 a n a l o g i n p u t m u l t i p l e x e r the XRD8799 includes a 8-channel analog input multiplexer. the relationship between the clock, the multiplexer address, the wr and the output data is shown in figure 12. f i g u r e 12. mux a d d r e s s t i m i n g f i g u r e 13. a n a l o g mux t i m i n g 1.5 r e f e r e n c e v o l t a g e s the input/output relationship is a function of v ref : a in = v in - v ref(-) v ref = v ref(+) - v ref(-) data = 1024 * (a in /v ref ) a system can increase total gain by reducing v ref . clock data b. single sampling n n balance clock data a. continuous sampling n n+1 n n+1 50 w 10 pf av dd a in 80 w f s 10 pf 160 w 4 1 pf 10 pf channel selection 8 control r series 200 w r mux 200 w 1/2 [ v ref(+) + v ref(-) ] f s f b 1 pf + wr clock db0-db9 t clks2 t wr t clkh2 address t as t ah sample n old address sample m new address sample m+1 n-2 valid n-1 valid old address n valid old address m valid new address note: t clks2 = t clkh2 = 0 a2, a1, a0 muxen (internal signal) t as t ah wr t wr t muxen1
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 13 1.6 d i g i t a l i n t e r f a c e s the logic encodes the outputs of the comparators in- to a binary code and latches the data in a d-type flip- flop for output. the functional equivalent of the XRD8799 (figure 14) is composed of: 1. delay stage (t ap ) from the clock to the sampling phase (f s ). 2. an ideal analog switch which samples v in . 3. an ideal a/d which tracks and converts v in with no delay. 4. a series of two dff's with specified hold (t hld ) and delay (t dl ) times. t ap , t hl d and t dl are specified in the electrical charac- teristics table. 1.7 p o w e r d o w n figure 15 shows the relationship between the clock, sampled v in to output data relationship and the effect of power down. f i g u r e 14. XRD8799 f u n c t i o n a l e q u i v a l e n t c i r - c u i t a n d i n t e r f a c e t i m i n g f i g u r e 15. p o w e r d o w n t i m i n g d i a g r a m f v in s a/d XRD8799 clk db9-db0 n n+1 n-1 n t dl t hld d q d q db9-db0 clk v in t ap n-2 valid db0-db9 clk v in pd i dd , iv ref(+) sample n sample m sample m+1 n-1 valid n valid m valid t clks1 t clkh1 t pd t pu
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 14 2.0 application notes f i g u r e 16. t y p i c a l c i r c u i t c o n n e c t i o n s the following information will be useful in maximizing the performance of the XRD8799. 1. all signals should not exceed av dd +0.5 v or agnd -0.5 v or dv dd +0.5 v or dgnd -0.5 v. 2. any input pin which can see a value outside the absolute maximum ratings (av dd or dv dd +0.5 v or agnd -0.5 v) should be protected by diode clamps (hp5082-2835) from input pin to the sup- plies. all XRD8799 inputs have input protection diodes which will protect the device from short transients outside the supply ranges. 3. the design of a pc board will affect the accuracy of XRD8799. use of wire wrap is not recom- mended. 4. the analog input signal (v in ) is quite sensitive and should be properly routed and terminated. it should be shielded from the clock and digital out- puts so as to minimize cross coupling and noise pickup. 5. the analog input should be driven by a low impedance (less than 50 w ). 6. analog and digital ground planes should be sub- stantial and common at one point only. the ground plane should act as a shield for parasitics and not a return path for signals. to reduce noise levels, use separate low impedance ground paths. dgnd should not be shared with other digital circuitry . if separate low impedance paths cannot be provided, dgnd should be connected to agnd next to the XRD8799. 7. dv dd should not be shared with other digital cir- cuitry to avoid conversion errors caused by digital supply transients. dv dd for the XRD8799 should be connected to av dd next to the XRD8799. 8. dv dd and av dd are connected inside the XRD8799. dgnd and agnd are connected internally. 9. each power supply and reference voltage pin should be decoupled with a ceramic (0.1 m f) and a tantalum (10 m f) capacitor as close to the device as possible. 10. the digital output should not drive long wires. the capacitive coupling and reflection will con- tribute noise to the conversion. when driving dis- tant loads, buffers should be used. 100 w resis- tors in series with the digital outputs in some applications reduces the digital output disruption of a in . ofw clk db9 - db0 oe agnd dgnd (substrate) XRD8799 a in1 v ref(+) v ref(-) 3/4 r 1/4 r buffer av dd dv dd c 1d, c 2d c 1a, c 2a c 1 = 4.7 or 10 m f tantalum c 2 = 0.1 m f chip cap or low inductance cap r t = clock transmission line termination reference voltage source v ref1(-) a in c 1 c 2 c 1 c 2 c 1 c 2 + - +5 v r t 1 of 8 a in8 z < 100 w resistive isolation of 50 to 100 w wr clk a2 a1 a0
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 15 f i g u r e 17. e x a m p l e o f a r e f e r e n c e v o l t a g e s o u r c e f i g u r e 18. 5v a n a l o g i n p u t for r = 5k use beckman instruments #694-3-r10k resistor array or equivalent. n o t e : high r values affect the input bw of adc due to the (r * c in of adc) time constant. therefore, for different applica- tions the r value needs to be selected as a trade-off between a in settling time and power dissipation. 0.1 m f mp5010 +5v + - + - 5k 100k v ref(+) v in + - r r a in1 v ref(-) + 5v +5v +5v db0 agnd av dd 1 of 8 a in8
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 16 f i g u r e 19. 10v a n a l o g i n p u t for r = 5k use beckman instruments #694-3-r10k resistor array or equivalent. n o t e : high r values affect the input bw of adc due to the (r * c in of adc) time constant. therefore, for different applica- tions the r value needs to be selected as a trade-off between a in settling time and power dissipation. f i g u r e 20. a/d l a d d e r a n d a in w i t h p r o g r a m m e d c o n t r o l ( o f v ref(+) , v ref(-) , 1/4 a n d 3/4 tap.) v ref(+) v in + - 2r r a in1 v ref(-) + 10v +5v +5v db0 agnd av dd 2r 1 of 8 a in8 v in + - @ power down write values to dac 3, 2, 1 = dac 4 to minimize power consumption. only a in and ladder detail shown. dac4 dac3 dac2 dac1 XRD8799 v ref(+) 3/4 1/4 v ref(+) v ref1(-) dac0 dac7 + - a in8 a in1 mp7641 mp7226 v in
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 17 f i g u r e 21. dnl v s . s a m p l i n g f r e q u e n c y f i g u r e 22. inl v s . s a m p l i n g f r e q u e n c y -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0.1 1.0 10.0 f s (mhz) dnl(lsb) v dd = 5v v ref(+) = 4.6v v ref(-) = 0v pos. dnl neg. dnl -4 -3 -2 -1 0 1 2 3 4 0.10 1.00 10.00 f s (mhz) inl(lsb) pos. inl neg. inl v dd = 5v v ref(+) = 4.6v v ref(-) = 0v
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 18 f i g u r e 23. s u p p l y c u r r e n t v s . s a m p l i n g f r e q u e n c y f i g u r e 24. b e s t f i t inl v s . r e f e r e n c e v o l t a g e 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 0.0 2.0 4.0 6.0 8.0 10.0 f s (mhz) i dd (ma) v dd = 5v v ref(+) = 4.6v v ref(-) = 0v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v ref(v) inl(lsb) v dd = 5v f s = 2mhz
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 19 f i g u r e 25. dnl v s . r e f e r e n c e v o l t a g e f i g u r e 26. s u p p l y c u r r e n t v s . t e m p e r a t u r e -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v ref(v) dnl(lsb) pos. dnl neg. dnl v dd = 5v f s = 2mhz 0 2 4 6 8 10 -60 -40 -20 0 20 40 60 80 100 temperature(c) i dd (ma) v dd = 5v v ref(+) = 4.6v v ref(-) = 0v f s = 2mhz
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 20 f i g u r e 27. dnl v s . t e m p e r a t u r e f i g u r e 28. r e f e r e n c e r e s i s t a n c e v s .t e m p e r a t u r e -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -60 -40 -20 0 20 40 60 80 100 temperature(c) dnl(lsb) v dd = 5v v ref(+) = 4.6v v ref(-) = 0v f s = 2mhz pos. dnl neg. dnl 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 -60 -40 -20 0 20 40 60 80 100 temperature(c) ref. resistance(kohm) v dd = 5v v ref(+) = 4.6v v ref(-) = 0v f s = 2mhz
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 21 f i g u r e 29. inl @ 2msps -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 0 128 256 384 512 640 768 896 1024 code lsb v dd = 5v v ref (+) = 4.6v v ref(-) = 0v
xr xr XRD8799 low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 22 note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.072 0.093 1.82 2.45 a 1 0.001 0.010 0.02 0.25 a 2 0.071 0.087 1.80 2.20 b 0.011 0.018 0.29 0.45 c 0.004 0.009 0.11 0.23 d 0.510 0.530 12.95 13.45 d 1 0.390 0.398 9.90 10.10 e 0.0315 bsc 0.80 bsc l 0.029 0.040 0.73 1.03 a 0 7 0 7 33 23 22 12 1 11 34 44 d d 1 d d 1 b e a a 2 a 1 a seating plane l c 44 lead plastic quad flat pack (10 mm x 10 mm qfp, 1.60 mm form) rev. 2.00
XRD8799 xr xr low power, 2 msps, 10-bit, a/d converter with 8-channel mux rev. 1.00 23 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any cir- cuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration pur- poses and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2001 exar corporation datasheet february 2001 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

▲Up To Search▲

Price & Availability of XRD8799

	To Download XRD8799 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .